shift4.v (307B)
1 module shift4(d, clr, clk, shf, q); 2 input d; 3 input clr; 4 input clk; 5 input shf; 6 output reg [3:0] q; 7 8 /* run on a rising clock signal */ 9 always @ (posedge clk) begin 10 if (clr) 11 q = 0; 12 else if (shf == 0) 13 q = (q << 1) | d; 14 else if (shf == 1) 15 q = (q >> 1) | d; 16 else 17 q = q; 18 end 19 endmodule