shift4_tb.v (1029B)
1 module shift4_tb; 2 reg tb_d; 3 reg tb_clr; 4 reg tb_clk; 5 reg tb_shf; 6 wire [3:0] tb_q; 7 8 shift4 shift4_tb( 9 .d (tb_d), 10 .clr (tb_clr), 11 .clk (tb_clk), 12 .shf (tb_shf), 13 .q (tb_q) 14 ); 15 16 /* switch clock values every 20 time units */ 17 always #20 tb_clk = ~tb_clk; 18 19 initial begin 20 $dumpfile("shift4.vcd"); 21 $dumpvars(0, shift4_tb); 22 23 $monitor("time=%3d, tb_d=%b, tb_clr=%b, tb_clk=%b, tb_shf=%b, tb_q=%b\n", 24 $time, tb_d, tb_clr, tb_clk, tb_shf, tb_q); 25 26 tb_clk <= 1; /* start clock */ 27 tb_shf <= 0; /* shift to the left */ 28 tb_d <= 1; /* data pin is 1 */ 29 30 /* initialize q to 0 */ 31 tb_clr <= 1; 32 #20 tb_clr <= 0; 33 34 /* 35 * q is currently 1, set the data pin to 0 so that we do not 36 * add 1 every time we shift 37 */ 38 #20 tb_d <= 0; 39 40 /* shift 2 times to the left */ 41 repeat (2) @ (posedge tb_clk) 42 ; 43 44 /* change shift direction */ 45 #20 tb_shf <= 1; 46 47 /* shift 2 times to the right */ 48 repeat (2) @ (posedge tb_clk) 49 ; 50 51 /* clear q */ 52 #20 tb_clr <= 1; 53 #20 tb_clr <= 0; 54 55 $finish; 56 end 57 endmodule