alu.v (506B)
1 module alu(clk, in_a, in_b, alu_op, mux_sel, alu_out, mux_out); 2 input clk; 3 input [31:0] in_a; 4 input [31:0] in_b; 5 input [1:0] alu_op; 6 input mux_sel; 7 output reg [31:0] alu_out; 8 output reg [31:0] mux_out; 9 10 always @ (posedge clk) begin 11 case (alu_op) 12 2'b00: alu_out = in_a & in_b; 13 2'b01: alu_out = in_a | in_b; 14 2'b10: alu_out = in_a + in_b; 15 2'b11: alu_out = in_a - in_b; 16 default: alu_out = 0; 17 endcase 18 if (mux_sel == 0) 19 mux_out = alu_out; 20 else 21 mux_out = in_b; 22 end 23 endmodule