alu_tb.v (942B)
1 module alu_tb; 2 reg tb_clk; 3 reg [31:0] tb_in_a; 4 reg [31:0] tb_in_b; 5 reg [1:0] tb_alu_op; 6 reg tb_mux_sel; 7 wire [31:0] tb_alu_out; 8 wire [31:0] tb_mux_out; 9 10 alu alu_tb( 11 .clk (tb_clk), 12 .in_a (tb_in_a), 13 .in_b (tb_in_b), 14 .alu_op (tb_alu_op), 15 .mux_sel (tb_mux_sel), 16 .alu_out (tb_alu_out), 17 .mux_out (tb_mux_out) 18 ); 19 20 always #20 tb_clk = ~tb_clk; 21 22 initial begin 23 $dumpfile("alu.vcd"); 24 $dumpvars(0, alu_tb); 25 26 $monitor("time=%3d, clk=%b, in_a=%b, in_b=%b, alu_op=%b, mux_sel=%b, alu_out=%b, mux_out=%b\n", 27 $time, tb_clk, tb_in_a, tb_in_b, tb_alu_op, tb_mux_sel, 28 tb_alu_out, tb_mux_out); 29 30 tb_clk <= 0; 31 32 tb_in_a <= 16'hffff; 33 tb_in_b <= 16'hc23a; 34 tb_alu_op <= 2'b01; 35 tb_mux_sel <= 0; 36 #40 37 38 tb_in_a <= 16'hab12; 39 tb_in_b <= 16'h12ba; 40 tb_alu_op <= 2'b10; 41 tb_mux_sel <= 0; 42 #40 43 44 tb_in_a <= 16'h12c5; 45 tb_in_b <= 16'hd145; 46 tb_alu_op <= 2'b11; 47 tb_mux_sel <= 1; 48 #40 49 50 $finish; 51 end 52 endmodule