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dec2to4en_tb.vhd (1287B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity dec2to4en_tb is
      5 end dec2to4en_tb;
      6 
      7 architecture behav of dec2to4en_tb is
      8 
      9 signal a1: std_logic_vector(1 downto 0);
     10 signal en1: std_logic;
     11 signal d1: std_logic_vector(3 downto 0);
     12 
     13 component dec2to4en is port (
     14         a: in std_logic_vector(1 downto 0);
     15         en: in std_logic;
     16         d: out std_logic_vector(3 downto 0)
     17 );
     18 end component;
     19 
     20 begin
     21         uut: dec2to4en port map (
     22                 a => a1,
     23                 en => en1,
     24                 d => d1
     25         );
     26 
     27         process begin
     28                 a1 <= "00";
     29                 en1 <= '0';
     30                 wait for 20 ps;
     31 
     32                 a1 <= "01";
     33                 en1 <= '0';
     34                 wait for 20 ps;
     35 
     36                 a1 <= "10";
     37                 en1 <= '0';
     38                 wait for 20 ps;
     39 
     40                 a1 <= "11";
     41                 en1 <= '0';
     42                 wait for 20 ps;
     43 
     44                 a1 <= "00";
     45                 en1 <= '1';
     46                 wait for 20 ps;
     47 
     48                 a1 <= "01";
     49                 en1 <= '1';
     50                 wait for 20 ps;
     51 
     52                 a1 <= "10";
     53                 en1 <= '1';
     54                 wait for 20 ps;
     55 
     56                 a1 <= "11";
     57                 en1 <= '1';
     58                 wait for 20 ps;
     59         end process;
     60 end behav;