uni

University stuff
git clone git://git.christosmarg.xyz/uni-assignments.git
Log | Files | Refs | README | LICENSE

mux2to1.vhd (281B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity mux2to1 is
      5 port (
      6         a, b, s: in bit;
      7         c: out bit
      8 );
      9 end mux2to1;
     10 
     11 architecture dataflow of mux2to1 is
     12 begin
     13         c <= a when s = '1' else b;
     14         --c <= (a and s) or (b and (not s)); -- logic form
     15 end dataflow;