mux4to1.vhd (592B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity mux4to1 is port ( 5 a: in std_logic_vector(3 downto 0); 6 s: in std_logic_vector(1 downto 0); 7 d: out std_logic 8 ); 9 end mux4to1; 10 11 architecture behav of mux4to1 is 12 begin 13 process (a, s) begin 14 case s is 15 when "00" => d <= a(0); 16 when "01" => d <= a(1); 17 when "10" => d <= a(2); 18 when "11" => d <= a(3); 19 when others => d <= 'X'; 20 end case; 21 end process; 22 end behav;