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mux4to1_tb.vhd (922B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity mux4to1_tb is
      5 end mux4to1_tb;
      6 
      7 architecture behav of mux4to1_tb is
      8 
      9 signal a1: std_logic_vector(3 downto 0);
     10 signal s1: std_logic_vector(1 downto 0);
     11 signal d1: std_logic;
     12 
     13 component mux4to1 port (
     14         a: in std_logic_vector(3 downto 0);
     15         s: in std_logic_vector(1 downto 0);
     16         d: out std_logic
     17 );
     18 end component;
     19 
     20 begin
     21         uut: mux4to1 port map (
     22                 a => a1,
     23                 s => s1,
     24                 d => d1
     25         );
     26 
     27         process begin
     28                 a1 <= "0000";
     29                 s1 <= "00";
     30                 wait for 20 ps;
     31 
     32                 a1 <= "0101";
     33                 s1 <= "01";
     34                 wait for 20 ps;
     35 
     36                 a1 <= "1010";
     37                 s1 <= "10";
     38                 wait for 20 ps;
     39 
     40                 a1 <= "1100";
     41                 s1 <= "11";
     42                 wait for 20 ps;
     43         end process;
     44 end behav;