mux_triple_2to1_tb.vhd (1574B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity mux_triple_2to1_tb is 5 end mux_triple_2to1_tb; 6 7 architecture behav of mux_triple_2to1_tb is 8 9 signal a1, b1: std_logic_vector(2 downto 0); 10 signal s1: std_logic; 11 signal d1: std_logic_vector(2 downto 0); 12 13 component mux_triple_2to1 port ( 14 a, b: in std_logic_vector(2 downto 0); 15 s: in std_logic; 16 d: out std_logic_vector(2 downto 0) 17 ); 18 end component; 19 20 begin 21 uut: mux_triple_2to1 port map ( 22 a => a1, 23 b => b1, 24 s => s1, 25 d => d1 26 ); 27 28 process begin 29 a1 <= "001"; 30 b1 <= "010"; 31 s1 <= '0'; 32 wait for 20 ps; 33 34 a1 <= "010"; 35 b1 <= "100"; 36 s1 <= '0'; 37 wait for 20 ps; 38 39 a1 <= "111"; 40 b1 <= "011"; 41 s1 <= '0'; 42 wait for 20 ps; 43 44 a1 <= "101"; 45 b1 <= "111"; 46 s1 <= '0'; 47 wait for 20 ps; 48 49 a1 <= "010"; 50 b1 <= "001"; 51 s1 <= '1'; 52 wait for 20 ps; 53 54 a1 <= "000"; 55 b1 <= "101"; 56 s1 <= '1'; 57 wait for 20 ps; 58 59 a1 <= "101"; 60 b1 <= "010"; 61 s1 <= '1'; 62 wait for 20 ps; 63 64 a1 <= "111"; 65 b1 <= "101"; 66 s1 <= '1'; 67 wait for 20 ps; 68 end process; 69 end behav;