uni

University stuff
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ff.vhd (208B)

      1 entity ff is port (
      2 	d: in bit;
      3 	clk: in bit;
      4 	q: out bit
      5 );
      6 end ff;
      7 
      8 architecture behav of ff is
      9 begin
     10 	process (clk) begin
     11 		if (clk 'event and clk = '1') then
     12 			q <= d;
     13 		end if;
     14 	end process;
     15 end behav;