ff_tb.vhd (723B)
1 entity ff_tb is 2 end ff_tb; 3 4 architecture behav of ff_tb is 5 6 signal d1: bit; 7 signal clk1: bit; 8 signal q1: bit; 9 10 component ff is port ( 11 d: in bit; 12 clk: in bit; 13 q: out bit 14 ); 15 end component; 16 17 begin 18 uut: ff port map ( 19 d => d1, 20 clk => clk1, 21 q => q1 22 ); 23 24 process begin 25 clk1 <= '1'; 26 wait for 150 ns; 27 clk1 <= '0'; 28 wait for 250 ns; 29 clk1 <= '1'; 30 wait for 150 ns; 31 clk1 <= '0'; 32 wait for 250 ns; 33 clk1 <= '1'; 34 wait for 150 ns; 35 clk1 <= '0'; 36 wait for 250 ns; 37 end process; 38 39 process begin 40 d1 <= '1'; 41 wait for 280 ns; 42 d1 <= '0'; 43 wait for 300 ns; 44 d1 <= '1'; 45 wait for 250 ns; 46 d1 <= '0'; 47 wait for 150 ns; 48 d1 <= '1'; 49 wait for 75 ns; 50 d1 <= '0'; 51 wait for 150 ns; 52 end process; 53 end behav;