uni

University stuff
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reg.vhd (357B)


      1 entity reg is port (
      2 	d: in bit_vector(3 downto 0);
      3 	clk: in bit;
      4 	clr: in bit;
      5 	q: out bit_vector(3 downto 0)
      6 );
      7 end reg;
      8 
      9 architecture struct of reg is
     10 component ffrst is port (
     11 	d: in bit;
     12 	clk: in bit;
     13 	rst: in bit;
     14 	q: out bit
     15 );
     16 end component;
     17 
     18 begin
     19 	u: for i in 0 to 3 generate
     20 		f: ffrst port map (d(i), clk, clr, q(i));
     21 	end generate;
     22 end struct;