reg_tb.vhd (688B)
1 entity reg_tb is 2 end reg_tb; 3 4 architecture behav of reg_tb is 5 6 signal d1: bit_vector(3 downto 0); 7 signal clk1: bit; 8 signal clr1: bit; 9 signal q1: bit_vector(3 downto 0); 10 11 component reg is port ( 12 d: in bit_vector(3 downto 0); 13 clk: in bit; 14 clr: in bit; 15 q: out bit_vector(3 downto 0) 16 ); 17 end component; 18 19 begin 20 uut: reg port map ( 21 d => d1, 22 clk => clk1, 23 clr => clr1, 24 q => q1 25 ); 26 27 process begin 28 clr1 <= '0'; 29 clk1 <= '0'; 30 d1 <= "0001"; 31 wait for 250 ns; 32 33 clr1 <= '1'; 34 clk1 <= '1'; 35 d1 <= "0001"; 36 wait for 250 ns; 37 38 clr1 <= '1'; 39 clk1 <= '0'; 40 d1 <= "0011"; 41 wait for 250 ns; 42 43 clr1 <= '1'; 44 clk1 <= '1'; 45 d1 <= "0101"; 46 wait for 250 ns; 47 end process; 48 end behav;