shift4.vhd (564B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity shift4 is port ( 5 d: in std_logic_vector(3 downto 0); 6 en: in std_logic; 7 load: in std_logic; 8 sin: in std_logic; 9 clk: in std_logic; 10 q: out std_logic_vector(3 downto 0) 11 ); 12 end shift4; 13 14 architecture behav of shift4 is 15 16 signal qq: std_logic_vector(3 downto 0); 17 18 begin 19 process (clk) begin 20 if (rising_edge(clk)) then 21 if (load = '1') then 22 q <= d; 23 elsif (en = '1') then 24 qq(0) <= qq(1); 25 qq(1) <= qq(2); 26 qq(2) <= qq(3); 27 qq(3) <= sin; 28 end if; 29 end if; 30 end process; 31 q <= qq; 32 end behav;