shift4_tb.vhd (843B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity shift4_tb is 5 end shift4_tb; 6 7 architecture behav of shift4_tb is 8 9 signal d1: std_logic_vector(3 downto 0); 10 signal en1: std_logic; 11 signal load1: std_logic; 12 signal sin1: std_logic; 13 signal clk1: std_logic; 14 signal q1: std_logic_vector(3 downto 0); 15 16 component shift4 is port ( 17 d: in std_logic_vector(3 downto 0); 18 en: in std_logic; 19 load: in std_logic; 20 sin: in std_logic; 21 clk: in std_logic; 22 q: out std_logic_vector(3 downto 0) 23 ); 24 end component; 25 26 begin 27 uut: shift4 port map ( 28 d => d1, 29 en => en1, 30 load => load1, 31 sin => sin1, 32 clk => clk1, 33 q => q1 34 ); 35 36 process begin 37 d1 <= "1011"; 38 load1 <= '1'; 39 en1 <= '0'; 40 sin1 <= '1'; 41 clk1 <= '1'; 42 wait for 250 ns; 43 44 d1 <= "1011"; 45 load1 <= '0'; 46 en1 <= '1'; 47 sin1 <= '0'; 48 clk1 <= '1'; 49 wait for 250 ns; 50 end process; 51 end behav;