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upcount_tb.vhd (550B)

      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity upcount_tb is
      5 end upcount_tb;
      6 
      7 architecture behav of upcount_tb is
      8 
      9 signal clk1: std_logic := '1';
     10 signal rst1: std_logic := '1';
     11 signal q1: std_logic_vector(1 downto 0);
     12 
     13 component upcount is port (
     14 	clk: in std_logic;
     15 	rst: in std_logic;
     16 	q: inout std_logic_vector(1 downto 0)
     17 );
     18 end component;
     19 
     20 begin
     21 	uut: upcount port map (
     22 		clk => clk1,
     23 		rst => rst1,
     24 		q => q1
     25 	);
     26 	
     27 	process begin
     28 		rst1 <= '0';
     29 		clk1 <= '0';
     30 		wait for 250 ns;
     31 
     32 		clk1 <= '1';
     33 		wait for 250 ns;
     34 	end process;
     35 end behav;