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regfile.vhd (718B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 use ieee.std_logic_unsigned.all;
      4 use ieee.numeric_std.all;
      5 
      6 entity regfile is
      7 generic (
      8 	dw:	natural := 4;
      9 	sz:	natural := 4;
     10 	addrw:	natural := 2
     11 );
     12 port (
     13 	a:	in std_logic_vector(dw-1 downto 0);
     14 	addr:	in std_logic_vector(addrw-1 downto 0);
     15 	we:	in std_logic;
     16 	clk:	in std_logic;
     17 	c:	out std_logic_vector(dw-1 downto 0)
     18 );
     19 end regfile;
     20 
     21 architecture behav of regfile is
     22 
     23 type regarr is array(sz-1 downto 0) of std_logic_vector(dw-1 downto 0);
     24 signal regf: regarr;
     25 
     26 begin
     27 	process (clk) begin
     28 		if (falling_edge(clk)) then
     29 			if (we = '1') then
     30 				regf(to_integer(unsigned(addr))) <= a;
     31 			end if;
     32 		end if;
     33 	end process;
     34 	c <= regf(to_integer(unsigned(addr)));
     35 end behav;