regfile_tb.vhd (1379B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity regfile_tb is 5 end regfile_tb; 6 7 architecture behav of regfile_tb is 8 9 component regfile is 10 generic ( 11 dw: natural := 4; 12 sz: natural := 4; 13 addrw: natural := 2 14 ); 15 port ( 16 a: in std_logic_vector(dw-1 downto 0); 17 addr: in std_logic_vector(addrw-1 downto 0); 18 we: in std_logic; 19 clk: in std_logic; 20 c: out std_logic_vector(dw-1 downto 0) 21 ); 22 end component; 23 24 signal s_dw: natural := 4; 25 signal s_sz: natural := 4; 26 signal s_addrw: natural := 2; 27 signal s_a: std_logic_vector(s_dw-1 downto 0); 28 signal s_addr: std_logic_vector(s_addrw-1 downto 0); 29 signal s_we: std_logic; 30 signal s_clk: std_logic; 31 signal s_c: std_logic_vector(s_dw-1 downto 0); 32 33 begin 34 uut: regfile port map ( 35 a => s_a, 36 addr => s_addr, 37 we => s_we, 38 clk => s_clk, 39 c => s_c 40 ); 41 42 process begin 43 s_we <= '1'; 44 s_clk <= '1'; 45 wait for 250 ns; 46 47 s_we <= '1'; 48 s_clk <= '0'; 49 s_addr <= "00"; 50 s_a <= "0101"; 51 wait for 250 ns; 52 53 s_we <= '1'; 54 s_clk <= '1'; 55 wait for 250 ns; 56 57 s_we <= '1'; 58 s_clk <= '0'; 59 s_addr <= "01"; 60 s_a <= "1101"; 61 wait for 250 ns; 62 63 s_we <= '1'; 64 s_clk <= '1'; 65 wait for 250 ns; 66 67 s_we <= '1'; 68 s_clk <= '0'; 69 s_addr <= "10"; 70 s_a <= "0010"; 71 wait for 250 ns; 72 73 s_we <= '1'; 74 s_clk <= '1'; 75 wait for 250 ns; 76 77 s_we <= '1'; 78 s_clk <= '0'; 79 s_addr <= "11"; 80 s_a <= "1001"; 81 wait for 250 ns; 82 end process; 83 end behav;