adder4.vhd (533B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use work.all; 4 5 entity adder4 is port ( 6 a, b: in std_logic_vector(3 downto 0); 7 cin: in std_logic; 8 s: out std_logic_vector(3 downto 0); 9 cout: out std_logic 10 ); 11 end adder4; 12 13 architecture struct of adder4 is 14 15 signal y: std_logic_vector(4 downto 0); 16 17 begin 18 y(0) <= cin; 19 cout <= y(4); 20 u: for i in 0 to 3 generate 21 p: entity work.fa(dataflow) port map (a(i), b(i), cin, s(i), cout => y(i+1)); 22 end generate; 23 end struct;