adder4_tb.vhd (1681B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity adder4_tb is 5 end adder4_tb; 6 7 architecture behav of adder4_tb is 8 9 signal a1, b1: std_logic_vector(3 downto 0); 10 signal cin1: std_logic; 11 signal s1: std_logic_vector(3 downto 0); 12 signal cout1: std_logic; 13 14 component adder4 is port ( 15 a, b: in std_logic_vector(3 downto 0); 16 cin: in std_logic; 17 s: out std_logic_vector(3 downto 0); 18 cout: out std_logic 19 ); 20 end component; 21 22 begin 23 uut: adder4 port map ( 24 a => a1, 25 b => b1, 26 cin => cin1, 27 s => s1, 28 cout => cout1 29 ); 30 31 process begin 32 a1 <= "0000"; 33 b1 <= "0000"; 34 cin1 <= '0'; 35 wait for 20 ps; 36 37 a1 <= "1111"; 38 b1 <= "1111"; 39 cin1 <= '0'; 40 wait for 20 ps; 41 42 a1 <= "1111"; 43 b1 <= "1111"; 44 cin1 <= '1'; 45 wait for 20 ps; 46 47 -- 3 + 5 (overflow) 48 a1 <= "0011"; 49 b1 <= "0101"; 50 cin1 <= '0'; 51 wait for 20 ps; 52 53 -- -2 + 3 54 -- 2 -> 0010 -> (2's complement) -> ~0010 | 0001 -> 55 -- 1101 | 0001 -> 1101 (+ cin) 56 a1 <= not "0010" or "0001"; 57 b1 <= "0011"; 58 cin1 <= '1'; 59 wait for 20 ps; 60 61 -- -8 + 7 (~1000 | 0001 + cin) 62 a1 <= not "1000" or "0001"; 63 b1 <= "0111"; 64 cin1 <= '1'; 65 wait for 20 ps; 66 end process; 67 end behav;