dec2to4.vhd (370B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity dec2to4 is port ( 5 a: in std_logic_vector(1 downto 0); 6 d: out std_logic_vector(3 downto 0) 7 ); 8 end dec2to4; 9 10 architecture dataflow of dec2to4 is 11 begin 12 d(0) <= not a(0) and not a(1); 13 d(1) <= not a(0) and a(1); 14 d(2) <= a(0) and not a(1); 15 d(3) <= a(0) and a(1); 16 end dataflow;