dec2to4_tb.vhd (733B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity dec2to4_tb is 5 end dec2to4_tb; 6 7 architecture behav of dec2to4_tb is 8 9 signal a1: std_logic_vector(1 downto 0); 10 signal d1: std_logic_vector(3 downto 0); 11 12 component dec2to4 is port ( 13 a: in std_logic_vector(1 downto 0); 14 d: out std_logic_vector(3 downto 0) 15 ); 16 end component; 17 18 begin 19 uut: dec2to4 port map ( 20 a => a1, 21 d => d1 22 ); 23 24 process begin 25 a1 <= "00"; 26 wait for 20 ps; 27 28 a1 <= "01"; 29 wait for 20 ps; 30 31 a1 <= "10"; 32 wait for 20 ps; 33 34 a1 <= "11"; 35 wait for 20 ps; 36 end process; 37 end behav;