dec4to16.vhd (1290B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity dec4to16 is port ( 5 a: in std_logic_vector(3 downto 0); 6 d: out std_logic_vector(15 downto 0) 7 ); 8 end dec4to16; 9 10 architecture dataflow of dec4to16 is 11 begin 12 d(0) <= not a(3) and not a(2) and not a(1) and not a(0); 13 d(1) <= not a(3) and not a(2) and not a(1) and a(0); 14 d(2) <= not a(3) and not a(2) and a(1) and not a(0); 15 d(3) <= not a(3) and not a(2) and a(1) and a(0); 16 d(4) <= not a(3) and a(2) and not a(1) and not a(0); 17 d(5) <= not a(3) and a(2) and not a(1) and a(0); 18 d(6) <= not a(3) and a(2) and a(1) and not a(0); 19 d(7) <= not a(3) and a(2) and a(1) and a(0); 20 d(8) <= a(3) and not a(2) and not a(1) and not a(0); 21 d(9) <= a(3) and not a(2) and not a(1) and a(0); 22 d(10) <= a(3) and not a(2) and a(1) and not a(0); 23 d(11) <= a(3) and not a(2) and a(1) and a(0); 24 d(12) <= a(3) and a(2) and not a(1) and not a(0); 25 d(13) <= a(3) and a(2) and not a(1) and a(0); 26 d(14) <= a(3) and a(2) and a(1) and not a(0); 27 d(15) <= a(3) and a(2) and a(1) and a(0); 28 end dataflow;