dec4to16_tb.vhd (1504B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity dec4to16_tb is 5 end dec4to16_tb; 6 7 architecture behav of dec4to16_tb is 8 9 signal a1: std_logic_vector(3 downto 0); 10 signal d1: std_logic_vector(15 downto 0); 11 12 component dec4to16 is port ( 13 a: in std_logic_vector(3 downto 0); 14 d: out std_logic_vector(15 downto 0) 15 ); 16 end component; 17 18 begin 19 uut: dec4to16 port map ( 20 a => a1, 21 d => d1 22 ); 23 24 process begin 25 a1 <= "0000"; 26 wait for 20 ps; 27 28 a1 <= "0001"; 29 wait for 20 ps; 30 31 a1 <= "0010"; 32 wait for 20 ps; 33 34 a1 <= "0011"; 35 wait for 20 ps; 36 37 a1 <= "0100"; 38 wait for 20 ps; 39 40 a1 <= "0101"; 41 wait for 20 ps; 42 43 a1 <= "0110"; 44 wait for 20 ps; 45 46 a1 <= "0111"; 47 wait for 20 ps; 48 49 a1 <= "1000"; 50 wait for 20 ps; 51 52 a1 <= "1001"; 53 wait for 20 ps; 54 55 a1 <= "1010"; 56 wait for 20 ps; 57 58 a1 <= "1011"; 59 wait for 20 ps; 60 61 a1 <= "1100"; 62 wait for 20 ps; 63 64 a1 <= "1101"; 65 wait for 20 ps; 66 67 a1 <= "1110"; 68 wait for 20 ps; 69 70 a1 <= "1111"; 71 wait for 20 ps; 72 end process; 73 end behav;