uni

University stuff
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fa.vhd (271B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity fa is port (
      5         a, b, cin: in std_logic;
      6         s, cout: out std_logic
      7 );
      8 end fa;
      9 
     10 architecture dataflow of fa is
     11 begin
     12         s <= a xor b xor cin;
     13         cout <= (a and b) or (cin and (a xor b));
     14 end dataflow;