fa_tb.vhd (1432B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity fa_tb is 5 end fa_tb; 6 7 architecture behav of fa_tb is 8 9 signal a1, b1, cin1: std_logic; 10 signal s1, cout1: std_logic; 11 12 component fa is port ( 13 a, b, cin: in std_logic; 14 s, cout: out std_logic 15 ); 16 end component; 17 18 begin 19 uut: fa port map ( 20 a => a1, 21 b => b1, 22 cin => cin1, 23 s => s1, 24 cout => cout1 25 ); 26 27 process begin 28 a1 <= '0'; 29 b1 <= '0'; 30 cin1 <= '0'; 31 wait for 20 ps; 32 33 a1 <= '0'; 34 b1 <= '0'; 35 cin1 <= '1'; 36 wait for 20 ps; 37 38 a1 <= '0'; 39 b1 <= '1'; 40 cin1 <= '0'; 41 wait for 20 ps; 42 43 a1 <= '0'; 44 b1 <= '1'; 45 cin1 <= '1'; 46 wait for 20 ps; 47 48 a1 <= '1'; 49 b1 <= '0'; 50 cin1 <= '0'; 51 wait for 20 ps; 52 53 a1 <= '1'; 54 b1 <= '0'; 55 cin1 <= '1'; 56 wait for 20 ps; 57 58 a1 <= '1'; 59 b1 <= '1'; 60 cin1 <= '0'; 61 wait for 20 ps; 62 63 a1 <= '1'; 64 b1 <= '1'; 65 cin1 <= '1'; 66 wait for 20 ps; 67 end process; 68 end behav;