ha_tb.vhd (776B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity ha_tb is 5 end ha_tb; 6 7 architecture behav of ha_tb is 8 9 signal a1, b1: bit; 10 signal s1, c1: bit; 11 12 component ha is port ( 13 a, b: in bit; 14 s, c: out bit 15 ); 16 end component; 17 18 begin 19 uut: ha port map ( 20 a => a1, 21 b => b1, 22 s => s1, 23 c => c1 24 ); 25 26 process begin 27 a1 <= '0'; 28 b1 <= '0'; 29 wait for 20 ps; 30 31 a1 <= '0'; 32 b1 <= '1'; 33 wait for 20 ps; 34 35 a1 <= '1'; 36 b1 <= '0'; 37 wait for 20 ps; 38 39 a1 <= '1'; 40 b1 <= '1'; 41 wait for 20 ps; 42 end process; 43 end behav;