ffrst.vhd (287B)
1 entity ffrst is port ( 2 d: in bit; 3 clk: in bit; 4 rst: in bit; 5 q: out bit 6 ); 7 end ffrst; 8 9 architecture behav of ffrst is 10 begin 11 process (clk, rst) begin 12 if (rst = '0') then 13 q <= '0'; 14 elsif (clk 'event and clk = '1') then 15 q <= d; 16 end if; 17 end process; 18 end behav;