ffrst_tb.vhd (869B)
1 entity ffrst_tb is 2 end ffrst_tb; 3 4 architecture behav of ffrst_tb is 5 6 signal d1: bit; 7 signal clk1: bit; 8 signal rst1: bit; 9 signal q1: bit; 10 11 component ffrst is port ( 12 d: in bit; 13 clk: in bit; 14 rst: in bit; 15 q: out bit 16 ); 17 end component; 18 19 begin 20 uut: ffrst port map ( 21 d => d1, 22 clk => clk1, 23 rst => rst1, 24 q => q1 25 ); 26 27 process begin 28 rst1 <= '1'; 29 clk1 <= '1'; 30 wait for 150 ns; 31 clk1 <= '0'; 32 wait for 250 ns; 33 rst1 <= '0'; -- reset now is 0 so q is always 0 now 34 clk1 <= '1'; 35 wait for 150 ns; 36 clk1 <= '0'; 37 wait for 250 ns; 38 rst1 <= '1'; 39 clk1 <= '1'; 40 wait for 150 ns; 41 clk1 <= '0'; 42 wait for 250 ns; 43 end process; 44 45 process begin 46 d1 <= '1'; 47 wait for 280 ns; 48 d1 <= '0'; 49 wait for 300 ns; 50 d1 <= '1'; 51 wait for 250 ns; 52 d1 <= '0'; 53 wait for 150 ns; 54 d1 <= '1'; 55 wait for 75 ns; 56 d1 <= '0'; 57 wait for 150 ns; 58 end process; 59 end behav;