shiftn.vhd (628B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity shiftn is 5 generic (n: integer := 8); 6 port ( 7 d: in std_logic_vector(n - 1 downto 0); 8 en: in std_logic; 9 load: in std_logic; 10 sin: in std_logic; 11 clk: in std_logic; 12 q: out std_logic_vector(n - 1 downto 0) 13 ); 14 end shiftn; 15 16 architecture behav of shiftn is 17 18 signal qq: std_logic_vector(n - 1 downto 0); 19 20 begin 21 process (clk) begin 22 if (rising_edge(clk)) then 23 if (load = '1') then 24 q <= d; 25 elsif (en = '1') then 26 u: for i in 0 to n - 2 loop 27 qq(i) <= qq(i + 1); 28 end loop; 29 qq(n - 1) <= sin; 30 end if; 31 end if; 32 end process; 33 q <= qq; 34 end behav;