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regfile_ext.vhd (1046B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 use ieee.std_logic_unsigned.all;
      4 use ieee.numeric_std.all;
      5 
      6 entity regfile_ext is
      7 generic (
      8 	dw:	natural := 4;
      9 	sz:	natural := 4;
     10 	addrw:	natural := 2
     11 );
     12 port (
     13 	a:	in std_logic_vector(dw-1 downto 0);
     14 	raddr1:	in std_logic_vector(addrw-1 downto 0);
     15 	raddr2:	in std_logic_vector(addrw-1 downto 0);
     16 	waddr:	in std_logic_vector(addrw-1 downto 0);
     17 	we:	in std_logic;
     18 	clk:	in std_logic;
     19 	rst:	in std_logic;
     20 	b:	out std_logic_vector(dw-1 downto 0);
     21 	c:	out std_logic_vector(dw-1 downto 0)
     22 );
     23 end regfile_ext;
     24 
     25 architecture behav of regfile_ext is
     26 
     27 type regarr is array(sz-1 downto 0) of std_logic_vector(dw-1 downto 0);
     28 signal regf: regarr;
     29 
     30 begin
     31 	process (clk) begin
     32 		if (rst = '1') then
     33 			regf(0) <= "0000";
     34 			regf(1) <= "0000";
     35 			regf(2) <= "0000";
     36 			regf(3) <= "0000";
     37 		elsif (falling_edge(clk)) then
     38 			if (we = '1') then
     39 				regf(to_integer(unsigned(waddr))) <= a;
     40 			end if;
     41 		end if;
     42 	end process;
     43 	b <= regf(to_integer(unsigned(raddr1)));
     44 	c <= regf(to_integer(unsigned(raddr2)));
     45 end behav;