regfile_ext_tb.vhd (2104B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity regfile_ext_tb is 5 end regfile_ext_tb; 6 7 architecture behav of regfile_ext_tb is 8 9 component regfile_ext is 10 generic ( 11 dw: natural := 4; 12 sz: natural := 4; 13 addrw: natural := 2 14 ); 15 port ( 16 a: in std_logic_vector(dw-1 downto 0); 17 raddr1: in std_logic_vector(addrw-1 downto 0); 18 raddr2: in std_logic_vector(addrw-1 downto 0); 19 waddr: in std_logic_vector(addrw-1 downto 0); 20 we: in std_logic; 21 clk: in std_logic; 22 rst: in std_logic; 23 b: out std_logic_vector(dw-1 downto 0); 24 c: out std_logic_vector(dw-1 downto 0) 25 ); 26 end component; 27 28 signal s_dw: natural := 4; 29 signal s_sz: natural := 4; 30 signal s_addrw: natural := 2; 31 signal s_a: std_logic_vector(s_dw-1 downto 0); 32 signal s_raddr1:std_logic_vector(s_addrw-1 downto 0); 33 signal s_raddr2:std_logic_vector(s_addrw-1 downto 0); 34 signal s_waddr: std_logic_vector(s_addrw-1 downto 0); 35 signal s_we: std_logic; 36 signal s_clk: std_logic; 37 signal s_rst: std_logic; 38 signal s_b: std_logic_vector(s_dw-1 downto 0); 39 signal s_c: std_logic_vector(s_dw-1 downto 0); 40 41 begin 42 uut: regfile_ext port map ( 43 a => s_a, 44 raddr1 => s_raddr1, 45 raddr2 => s_raddr2, 46 waddr => s_waddr, 47 we => s_we, 48 clk => s_clk, 49 rst => s_rst, 50 b => s_b, 51 c => s_c 52 ); 53 54 process begin 55 s_we <= '1'; 56 s_clk <= '1'; 57 s_rst <= '1'; 58 wait for 250 ns; 59 60 s_we <= '1'; 61 s_clk <= '0'; 62 s_rst <= '0'; 63 s_raddr1 <= "00"; 64 s_raddr2 <= "00"; 65 s_waddr <= "00"; 66 s_a <= "0101"; 67 wait for 250 ns; 68 69 s_we <= '1'; 70 s_clk <= '1'; 71 s_rst <= '1'; 72 wait for 250 ns; 73 74 s_we <= '1'; 75 s_clk <= '0'; 76 s_rst <= '0'; 77 s_raddr1 <= "01"; 78 s_raddr2 <= "01"; 79 s_waddr <= "01"; 80 s_a <= "1010"; 81 wait for 250 ns; 82 83 s_we <= '1'; 84 s_clk <= '1'; 85 s_rst <= '1'; 86 wait for 250 ns; 87 88 s_we <= '1'; 89 s_clk <= '0'; 90 s_rst <= '0'; 91 s_raddr1 <= "10"; 92 s_raddr2 <= "10"; 93 s_waddr <= "10"; 94 s_a <= "0000"; 95 wait for 250 ns; 96 97 s_we <= '1'; 98 s_clk <= '1'; 99 s_rst <= '1'; 100 wait for 250 ns; 101 102 s_we <= '1'; 103 s_clk <= '0'; 104 s_rst <= '0'; 105 s_raddr1 <= "11"; 106 s_raddr2 <= "11"; 107 s_waddr <= "11"; 108 s_a <= "1111"; 109 wait for 250 ns; 110 end process; 111 end behav;