alu4.vhd (924B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity alu4 is port ( 6 alu_in1: in std_logic_vector(3 downto 0); 7 alu_in2: in std_logic_vector(3 downto 0); 8 alu_ctrl: in std_logic_vector(3 downto 0); 9 alu_out: out std_logic_vector(3 downto 0); 10 alu_zero: out std_logic 11 ); 12 end alu4; 13 14 architecture behav of alu4 is 15 signal sig: std_logic_vector(3 downto 0); 16 17 begin 18 process (alu_ctrl) begin 19 case alu_ctrl is 20 when "0000" => sig <= alu_in1 and alu_in2; 21 when "0001" => sig <= alu_in1 or alu_in2; 22 when "0010" => 23 sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); 24 when "0110" => 25 sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); 26 when "0111" => 27 if (alu_in1 < alu_in2) then 28 sig <= "0001"; 29 else 30 sig <= "0000"; 31 end if; 32 when others => sig <= (others => 'X'); 33 end case; 34 end process; 35 alu_zero <= '1' when sig = "0000" else '0'; 36 alu_out <= sig; 37 end behav;