alu4_tb.vhd (1311B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity alu4_tb is 5 end alu4_tb; 6 7 architecture behav of alu4_tb is 8 component alu4 is port ( 9 alu_in1: in std_logic_vector(3 downto 0); 10 alu_in2: in std_logic_vector(3 downto 0); 11 alu_ctrl: in std_logic_vector(3 downto 0); 12 alu_out: out std_logic_vector(3 downto 0); 13 alu_zero: out std_logic 14 ); 15 end component; 16 17 signal s_alu_in1: std_logic_vector(3 downto 0); 18 signal s_alu_in2: std_logic_vector(3 downto 0); 19 signal s_alu_ctrl: std_logic_vector(3 downto 0); 20 signal s_alu_out: std_logic_vector(3 downto 0); 21 signal s_alu_zero: std_logic; 22 23 begin 24 uut: alu4 port map ( 25 alu_in1 => s_alu_in1, 26 alu_in2 => s_alu_in2, 27 alu_ctrl => s_alu_ctrl, 28 alu_out => s_alu_out, 29 alu_zero => s_alu_zero 30 ); 31 32 process begin 33 s_alu_in1 <= "0010"; 34 s_alu_in2 <= "0100"; 35 s_alu_ctrl <= "0010"; 36 wait for 250 ns; 37 38 s_alu_in1 <= "0100"; 39 s_alu_in2 <= "1111"; 40 s_alu_ctrl <= "0000"; 41 wait for 250 ns; 42 43 s_alu_in1 <= "0100"; 44 s_alu_in2 <= "1111"; 45 s_alu_ctrl <= "0001"; 46 wait for 250 ns; 47 48 s_alu_in1 <= "0100"; 49 s_alu_in2 <= "0010"; 50 s_alu_ctrl <= "0110"; 51 wait for 250 ns; 52 53 s_alu_in1 <= "0100"; 54 s_alu_in2 <= "0110"; 55 s_alu_ctrl <= "0110"; 56 wait for 250 ns; 57 58 s_alu_in1 <= "0100"; 59 s_alu_in2 <= "0110"; 60 s_alu_ctrl <= "0111"; 61 wait for 250 ns; 62 end process; 63 end behav;