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mux2to1gen.vhd (354B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity mux2to1gen is
      5 generic (
      6 	sz: 	natural := 4
      7 );
      8 port (
      9 	a: 	in std_logic_vector(sz-1 downto 0);
     10 	b: 	in std_logic_vector(sz-1 downto 0);
     11 	s: 	in std_logic;
     12 	c: 	out std_logic_vector(sz-1 downto 0)
     13 );
     14 end mux2to1gen;
     15 
     16 architecture dataflow of mux2to1gen is
     17 begin
     18 	c <= a when s = '1' else b;
     19 end dataflow;