uni

University stuff
git clone git://git.christosmarg.xyz/uni-assignments.git
Log | Files | Refs | README | LICENSE

mux2to1gen_tb.vhd (802B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity mux2to1gen_tb is
      5 end mux2to1gen_tb;
      6 
      7 architecture behav of mux2to1gen_tb is
      8 
      9 signal s_sz: 	natural := 4;
     10 signal s_a:	std_logic_vector(s_sz-1 downto 0);
     11 signal s_b:	std_logic_vector(s_sz-1 downto 0);
     12 signal s_s:	std_logic;
     13 signal s_c:	std_logic_vector(s_sz-1 downto 0);
     14 
     15 component mux2to1gen is
     16 generic (
     17 	sz:	natural := 4
     18 );
     19 port (
     20 	a:	in std_logic_vector(sz-1 downto 0);
     21 	b:	in std_logic_vector(sz-1 downto 0);
     22 	s: 	in std_logic;
     23 	c:	out std_logic_vector(sz-1 downto 0)
     24 );
     25 end component;
     26 
     27 begin
     28 	uut: mux2to1gen port map (
     29 		a => s_a,
     30 		b => s_b,
     31 		s => s_s,
     32 		c => s_c
     33 	);
     34 
     35 	process begin
     36 		s_a <= "0000";
     37 		s_b <= "1101";
     38 		s_s <= '0';
     39 		wait for 250 ns;
     40 
     41 		s_a <= "0000";
     42 		s_b <= "1101";
     43 		s_s <= '1';
     44 		wait for 250 ns;
     45 	end process;
     46 end behav;