alu_tb.vhd (1325B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity alu_tb is 6 end alu_tb; 7 8 architecture behav of alu_tb is 9 10 signal s_dw: natural := 4; 11 signal s_alu_in1: std_logic_vector(s_dw-1 downto 0); 12 signal s_alu_in2: std_logic_vector(s_dw-1 downto 0); 13 signal s_alu_ctrl: std_logic_vector(3 downto 0); 14 signal s_alu_out: std_logic_vector(s_dw-1 downto 0); 15 signal s_alu_zero: std_logic; 16 17 component alu is 18 generic ( 19 dw: natural := 4 20 ); 21 port ( 22 alu_in1: in std_logic_vector(dw-1 downto 0); 23 alu_in2: in std_logic_vector(dw-1 downto 0); 24 alu_ctrl: in std_logic_vector(3 downto 0); 25 alu_out: out std_logic_vector(dw-1 downto 0); 26 alu_zero: out std_logic 27 ); 28 end component; 29 30 begin 31 uut: alu port map ( 32 alu_in1 => s_alu_in1, 33 alu_in2 => s_alu_in2, 34 alu_ctrl => s_alu_ctrl, 35 alu_out => s_alu_out, 36 alu_zero => s_alu_zero 37 ); 38 39 process begin 40 s_alu_in1 <= "0010"; 41 s_alu_in2 <= "0100"; 42 s_alu_ctrl <= "0010"; 43 wait for 250 ns; 44 45 s_alu_in1 <= "0100"; 46 s_alu_in2 <= "1111"; 47 s_alu_ctrl <= "0000"; 48 wait for 250 ns; 49 50 s_alu_in1 <= "0100"; 51 s_alu_in2 <= "1111"; 52 s_alu_ctrl <= "0001"; 53 wait for 250 ns; 54 55 s_alu_in1 <= "0100"; 56 s_alu_in2 <= "0010"; 57 s_alu_ctrl <= "0110"; 58 wait for 250 ns; 59 60 s_alu_in1 <= "0100"; 61 s_alu_in2 <= "0110"; 62 s_alu_ctrl <= "0110"; 63 wait for 250 ns; 64 end process; 65 end behav;