alu.vhd (860B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity alu is 6 generic ( 7 sz: natural := 4 8 ); 9 port ( 10 alu_in1: in std_logic_vector(sz-1 downto 0); 11 alu_in2: in std_logic_vector(sz-1 downto 0); 12 alu_ctrl: in std_logic_vector(3 downto 0); 13 alu_out: out std_logic_vector(sz-1 downto 0); 14 alu_zero: out std_logic 15 ); 16 end alu; 17 18 architecture behav of alu is 19 signal sig: std_logic_vector(sz-1 downto 0); 20 21 begin 22 process (alu_ctrl) begin 23 case alu_ctrl is 24 when "0000" => sig <= alu_in1 and alu_in2; 25 when "0001" => sig <= alu_in1 or alu_in2; 26 when "0010" => 27 sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); 28 when "0110" => 29 sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); 30 when others => sig <= (others => 'X'); 31 end case; 32 end process; 33 alu_zero <= '1' when sig = "0000" else '0'; 34 alu_out <= sig; 35 end behav;