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alu_ctrl_test_alu.vhd (1215B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity alu_ctrl_test_alu is generic (
      5 	t_sz:		natural := 4
      6 );
      7 port (
      8 	t_funct:	in std_logic_vector(5 downto 0);
      9 	t_alu_op:	in std_logic_vector(1 downto 0);
     10 	t_alu_in1:	in std_logic_vector(t_sz-1 downto 0);
     11 	t_alu_in2:	in std_logic_vector(t_sz-1 downto 0);
     12 	t_alu_out:	out std_logic_vector(t_sz-1 downto 0);
     13 	t_alu_zero:	out std_logic
     14 );
     15 end alu_ctrl_test_alu;
     16 
     17 architecture struct of alu_ctrl_test_alu is
     18 
     19 signal s_ctrl:		std_logic_vector(3 downto 0);
     20 
     21 component alu_ctrl is port (
     22 	funct:		in std_logic_vector(5 downto 0);
     23 	alu_op:		in std_logic_vector(1 downto 0);
     24 	op:		out std_logic_vector(3 downto 0)
     25 );
     26 end component;
     27 
     28 component alu is generic (
     29 	sz:		natural := 4
     30 );
     31 port (
     32 	alu_in1:	in std_logic_vector(sz-1 downto 0);
     33 	alu_in2:	in std_logic_vector(sz-1 downto 0);
     34 	alu_ctrl:	in std_logic_vector(3 downto 0);
     35 	alu_out:	out std_logic_vector(sz-1 downto 0);
     36 	alu_zero:	out std_logic
     37 );
     38 end component;
     39 
     40 begin
     41 	uut_alu_ctrl: alu_ctrl port map (
     42 		funct => t_funct,
     43 		alu_op => t_alu_op,
     44 		op => s_ctrl
     45 	);
     46 
     47 	uut_alu: alu port map (
     48 		alu_in1 => t_alu_in1,
     49 		alu_in2 => t_alu_in2,
     50 		alu_ctrl => s_ctrl,
     51 		alu_out => t_alu_out,
     52 		alu_zero => t_alu_zero
     53 	);
     54 end struct;