alu_ctrl_test_alu_tb.vhd (1663B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity alu_ctrl_test_alu_tb is 5 end alu_ctrl_test_alu_tb; 6 7 architecture behav of alu_ctrl_test_alu_tb is 8 9 signal s_sz: natural := 4; 10 signal s_t_funct: std_logic_vector(5 downto 0); 11 signal s_t_alu_op: std_logic_vector(1 downto 0); 12 signal s_t_alu_in1: std_logic_vector(s_sz-1 downto 0); 13 signal s_t_alu_in2: std_logic_vector(s_sz-1 downto 0); 14 signal s_t_alu_out: std_logic_vector(s_sz-1 downto 0); 15 signal s_t_alu_zero: std_logic; 16 17 component alu_ctrl_test_alu is generic ( 18 t_sz: natural := 4 19 ); 20 port ( 21 t_funct: in std_logic_vector(5 downto 0); 22 t_alu_op: in std_logic_vector(1 downto 0); 23 t_alu_in1: in std_logic_vector(t_sz-1 downto 0); 24 t_alu_in2: in std_logic_vector(t_sz-1 downto 0); 25 t_alu_out: out std_logic_vector(t_sz-1 downto 0); 26 t_alu_zero: out std_logic 27 ); 28 end component; 29 30 begin 31 uut: alu_ctrl_test_alu port map ( 32 t_funct => s_t_funct, 33 t_alu_op => s_t_alu_op, 34 t_alu_in1 => s_t_alu_in1, 35 t_alu_in2 => s_t_alu_in2, 36 t_alu_out => s_t_alu_out, 37 t_alu_zero => s_t_alu_zero 38 ); 39 40 process begin 41 s_t_alu_in1 <= "1100"; 42 s_t_alu_in2 <= "1100"; 43 44 s_t_alu_op <= "00"; 45 s_t_funct <= "001001"; 46 wait for 250 ns; 47 48 s_t_alu_op <= "00"; 49 s_t_funct <= "001010"; 50 wait for 250 ns; 51 52 s_t_alu_op <= "01"; 53 s_t_funct <= "100111"; 54 wait for 250 ns; 55 56 s_t_alu_op <= "10"; 57 s_t_funct <= "100000"; 58 wait for 250 ns; 59 60 s_t_alu_op <= "10"; 61 s_t_funct <= "100010"; 62 wait for 250 ns; 63 64 s_t_alu_op <= "10"; 65 s_t_funct <= "100100"; 66 wait for 250 ns; 67 68 s_t_alu_op <= "10"; 69 s_t_funct <= "100101"; 70 wait for 250 ns; 71 72 s_t_alu_op <= "10"; 73 s_t_funct <= "101010"; 74 wait for 250 ns; 75 end process; 76 end behav;