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alu_ctrl_tb.vhd (1068B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity alu_ctrl_tb is
      5 end alu_ctrl_tb;
      6 
      7 architecture behav of alu_ctrl_tb is
      8 
      9 signal s_funct:		std_logic_vector(5 downto 0);
     10 signal s_alu_op:	std_logic_vector(1 downto 0);
     11 signal s_op:		std_logic_vector(3 downto 0);
     12 
     13 component alu_ctrl is port (
     14 	funct:		in std_logic_vector(5 downto 0);
     15 	alu_op:		in std_logic_vector(1 downto 0);
     16 	op:		out std_logic_vector(3 downto 0)
     17 );
     18 end component;
     19 
     20 begin
     21 	uut: alu_ctrl port map (
     22 		funct => s_funct,
     23 		alu_op => s_alu_op,
     24 		op => s_op
     25 	);
     26 
     27 	process begin
     28 		s_alu_op <= "00";
     29 		s_funct <= "001001";
     30 		wait for 250 ns;
     31 
     32 		s_alu_op <= "00";
     33 		s_funct <= "001010";
     34 		wait for 250 ns;
     35 
     36 		s_alu_op <= "01";
     37 		s_funct <= "100111";
     38 		wait for 250 ns;
     39 
     40 		s_alu_op <= "10";
     41 		s_funct <= "100000";
     42 		wait for 250 ns;
     43 
     44 		s_alu_op <= "10";
     45 		s_funct <= "100010";
     46 		wait for 250 ns;
     47 
     48 		s_alu_op <= "10";
     49 		s_funct <= "100100";
     50 		wait for 250 ns;
     51 
     52 		s_alu_op <= "10";
     53 		s_funct <= "100101";
     54 		wait for 250 ns;
     55 
     56 		s_alu_op <= "10";
     57 		s_funct <= "101010";
     58 		wait for 250 ns;
     59 	end process;
     60 end behav;