ctrl.vhd (874B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity ctrl is port ( 5 funct: in std_logic_vector(5 downto 0); 6 reg_dst: out std_logic; 7 reg_wr: out std_logic; 8 alu_src: out std_logic; 9 branch: out std_logic; 10 mem_rd: out std_logic; 11 mem_wr: out std_logic; 12 mem_toreg: out std_logic; 13 alu_op: out std_logic_vector(1 downto 0) 14 ); 15 end ctrl; 16 17 architecture dataflow of ctrl is 18 begin 19 reg_dst <= '1' when funct = "000000" else '0'; 20 reg_wr <= '1' when funct = "000000" or funct = "100011" else '0'; 21 alu_src <= '1' when funct = "100011" or funct = "101011" else '0'; 22 branch <= '1' when funct = "000100" else '0'; 23 mem_rd <= '1' when funct = "100011" else '0'; 24 mem_wr <= '1' when funct = "101011" else '0'; 25 mem_toreg <= '1' when funct = "100011" else '0'; 26 with funct select 27 alu_op <= "10" when "000000", 28 "01" when "000100", 29 "00" when others; 30 end dataflow;