ctrl_tb.vhd (1161B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity ctrl_tb is 5 end ctrl_tb; 6 7 architecture behav of ctrl_tb is 8 9 signal s_funct: std_logic_vector(5 downto 0); 10 signal s_reg_dst: std_logic; 11 signal s_reg_wr: std_logic; 12 signal s_alu_src: std_logic; 13 signal s_branch: std_logic; 14 signal s_mem_rd: std_logic; 15 signal s_mem_wr: std_logic; 16 signal s_mem_toreg: std_logic; 17 signal s_alu_op: std_logic_vector(1 downto 0); 18 19 component ctrl is port ( 20 funct: in std_logic_vector(5 downto 0); 21 reg_dst: out std_logic; 22 reg_wr: out std_logic; 23 alu_src: out std_logic; 24 branch: out std_logic; 25 mem_rd: out std_logic; 26 mem_wr: out std_logic; 27 mem_toreg: out std_logic; 28 alu_op: out std_logic_vector(1 downto 0) 29 ); 30 end component; 31 32 begin 33 uut: ctrl port map ( 34 funct => s_funct, 35 reg_dst => s_reg_dst, 36 reg_wr => s_reg_wr, 37 alu_src => s_alu_src, 38 branch => s_branch, 39 mem_rd => s_mem_rd, 40 mem_wr => s_mem_wr, 41 mem_toreg => s_mem_toreg, 42 alu_op => s_alu_op 43 ); 44 45 process begin 46 s_funct <= "000000"; 47 wait for 250 ns; 48 49 s_funct <= "100011"; 50 wait for 250 ns; 51 52 s_funct <= "101011"; 53 wait for 250 ns; 54 55 s_funct <= "000100"; 56 wait for 250 ns; 57 end process; 58 end behav;