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shl2_tb.vhd (508B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity shl2_tb is
      5 end shl2_tb;
      6 
      7 architecture behav of shl2_tb is
      8 
      9 signal s_in1:	std_logic_vector(31 downto 0);
     10 signal s_d:	std_logic_vector(31 downto 0);
     11 
     12 component shl2 is port (
     13 	in1:	in std_logic_vector(31 downto 0);
     14 	d:	out std_logic_vector(31 downto 0)
     15 );
     16 end component;
     17 
     18 begin
     19 	uut: shl2 port map (
     20 		in1 => s_in1,
     21 		d => s_d
     22 	);
     23 
     24 	process begin
     25 		s_in1 <= x"0000aaaf";
     26 		wait for 250 ns;
     27 
     28 		s_in1 <= x"ffffaaaf";
     29 		wait for 250 ns;
     30 	end process;
     31 end behav;