shl2.vhd (243B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity shl2 is port ( 5 in1: in std_logic_vector(31 downto 0); 6 d: out std_logic_vector(31 downto 0) 7 ); 8 end shl2; 9 10 architecture dataflow of shl2 is 11 begin 12 d <= in1(29 downto 0) & "00"; 13 end dataflow;