datamem.vhd (713B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 use ieee.numeric_std.all; 5 6 entity datamem is port ( 7 clk: in std_logic; 8 addr: in std_logic_vector(5 downto 0); 9 we: in std_logic; 10 re: in std_logic; 11 writed: in std_logic_vector(31 downto 0); 12 readd: out std_logic_vector(31 downto 0) 13 ); 14 end datamem; 15 16 architecture behav of datamem is 17 18 type data_arr is array(0 to 63) of std_logic_vector(31 downto 0); 19 signal memfile: data_arr; 20 21 begin 22 process (clk) begin 23 if (clk'event and clk = '0') then 24 if we = '1' then 25 memfile(to_integer(unsigned(addr))) <= writed; 26 end if; 27 end if; 28 if re = '1' then 29 readd <= memfile(to_integer(unsigned(addr))); 30 end if; 31 end process; 32 end behav;