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instrmem_tb.vhd (642B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity instrmem_tb is
      5 end instrmem_tb;
      6 
      7 architecture behav of instrmem_tb is
      8 
      9 signal s_addr:	std_logic_vector(3 downto 0);
     10 signal s_c:	std_logic_vector(31 downto 0);
     11 
     12 component instrmem is port (
     13 	addr:	in std_logic_vector(3 downto 0);
     14 	c:	out std_logic_vector(31 downto 0)
     15 );
     16 end component;
     17 
     18 begin
     19 	uut: instrmem port map (
     20 		addr => s_addr,
     21 		c => s_c
     22 	);
     23 
     24 	process begin
     25 		s_addr <= "0001";
     26 		wait for 250 ns;
     27 
     28 		s_addr <= "0010";
     29 		wait for 250 ns;
     30 
     31 		s_addr <= "0110";
     32 		wait for 250 ns;
     33 
     34 		s_addr <= "1000";
     35 		wait for 250 ns;
     36 
     37 		s_addr <= "1010";
     38 		wait for 250 ns;
     39 	end process;
     40 end behav;