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datamem_tb.vhd (1768B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity datamem_tb is
      5 end datamem_tb;
      6 
      7 architecture behav of datamem_tb is
      8 
      9 signal s_clk:		std_logic;
     10 signal s_addr:		std_logic_vector(5 downto 0);
     11 signal s_we:		std_logic;
     12 signal s_re:		std_logic;
     13 signal s_writed:	std_logic_vector(31 downto 0);
     14 signal s_readd:		std_logic_vector(31 downto 0);
     15 
     16 component datamem is port (
     17 	clk:		in std_logic;
     18 	addr:		in std_logic_vector(5 downto 0);
     19 	we:		in std_logic;
     20 	re:		in std_logic;
     21 	writed:		in std_logic_vector(31 downto 0);
     22 	readd:		out std_logic_vector(31 downto 0)
     23 );
     24 end component;
     25 
     26 begin
     27 	uut: datamem port map (
     28 		clk => s_clk,
     29 		addr => s_addr,
     30 		we => s_we,
     31 		re => s_re,
     32 		writed => s_writed,
     33 		readd => s_readd
     34 	);
     35 
     36 	process begin
     37 		s_clk <= '0';
     38 		wait for 250 ns;
     39 
     40 		s_clk <= '1';
     41 		wait for 250 ns;
     42 
     43 		s_we <= '1';
     44 		s_re <= '0';
     45 		s_addr <= "000000";
     46 		s_writed <= "01010101010101010101010101010101";
     47 		wait for 250 ns;
     48 
     49 		s_clk <= '0';
     50 		wait for 250 ns;
     51 
     52 		s_clk <= '1';
     53 		wait for 250 ns;
     54 
     55 		s_addr <= "000001";
     56 		s_writed <= "11011101110111011101110111011101";
     57 		wait for 250 ns;
     58 
     59 		s_clk <= '0';
     60 		wait for 250 ns;
     61 
     62 		s_clk <= '1';
     63 		wait for 250 ns;
     64 
     65 		s_addr <= "000010";
     66 		s_writed <= "00100010001000100010001000100010";
     67 		wait for 250 ns;
     68 
     69 		s_clk <= '0';
     70 		wait for 250 ns;
     71 
     72 		s_clk <= '1';
     73 		wait for 250 ns;
     74 
     75 		s_addr <= "000011";
     76 		s_writed <= "10011001100110011001100110011001";
     77 		wait for 250 ns;
     78 
     79 		s_clk <= '0';
     80 		wait for 250 ns;
     81 
     82 		s_clk <= '1';
     83 		wait for 250 ns;
     84 
     85 		s_we <= '0';
     86 		s_re <= '1';
     87 		s_addr <= "000000";
     88 		wait for 250 ns;
     89 
     90 		s_clk <= '0';
     91 		wait for 250 ns;
     92 
     93 		s_clk <= '1';
     94 		wait for 250 ns;
     95 
     96 		s_addr <= "000001";
     97 		wait for 250 ns;
     98 
     99 		s_clk <= '0';
    100 		wait for 250 ns;
    101 
    102 		s_clk <= '1';
    103 		wait for 250 ns;
    104 	end process;
    105 end behav;