reg.vhd (545B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity reg is 5 generic ( 6 sz: natural := 4 7 ); 8 port ( 9 d: in std_logic_vector(sz-1 downto 0); 10 rst: in std_logic; 11 clk: in std_logic; 12 q: out std_logic_vector(sz-1 downto 0) 13 ); 14 end reg; 15 16 architecture behav of reg is 17 18 -- We want to automatically initialize the vector no matter its size. 19 signal s_init: std_logic_vector(sz-1 downto 0) := (others => '0'); 20 21 begin 22 process (rst, clk) begin 23 if (rst = '0') then 24 q <= s_init; 25 elsif (rising_edge(clk)) then 26 q <= d; 27 end if; 28 end process; 29 end behav;