regfile.vhd (752B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 use ieee.numeric_std.all; 5 6 entity regfile is 7 generic ( 8 sz: natural := 4; 9 addrw: natural := 3 10 ); 11 port ( 12 idata: in std_logic_vector(sz-1 downto 0); 13 addr: in std_logic_vector(addrw-1 downto 0); 14 we: in std_logic; 15 clk: in std_logic; 16 odata: out std_logic_vector(sz-1 downto 0) 17 ); 18 end regfile; 19 20 architecture behav of regfile is 21 22 signal arrsz: natural := 4; 23 type regarr is array(arrsz-1 downto 0) of std_logic_vector(sz-1 downto 0); 24 signal regf: regarr; 25 26 begin 27 process (clk) begin 28 if (clk'event and clk = '0') then 29 if (we = '1') then 30 regf(to_integer(unsigned(addr))) <= idata; 31 end if; 32 end if; 33 end process; 34 odata <= regf(to_integer(unsigned(addr))); 35 end behav;